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Minimizing and Exploiting Leakage in VLSI Design - Nikhil Jayakumar; Suganth Paul; Rajesh Garg
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Nikhil Jayakumar; Suganth Paul; Rajesh Garg:

Minimizing and Exploiting Leakage in VLSI Design - nuovo livro

ISBN: 9781441909503

Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for p… mais…

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Minimizing and Exploiting Leakage in VLSI Design - Nikhil Jayakumar; Suganth Paul; Rajesh Garg
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Nikhil Jayakumar; Suganth Paul; Rajesh Garg:

Minimizing and Exploiting Leakage in VLSI Design - nuovo livro

ISBN: 9781441909503

Engineering; Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design ASIC, EDA, Electronic Design Automation, Leakage, Low Power Design, Sub-threshold logic, Transistor, VL… mais…

  - This book presents two techniques to reduce leakage power in digital VLSI ICs. The first reduces leakage through the selective use of high threshold voltage sleep transistors, while the second by applying the optimal Reverse Body Bias voltage. Custos de envio:zzgl. Versandkosten., mais custos de envio
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Minimizing and Exploiting Leakage in VLSI Design - Nikhil Jayakumar; Suganth Paul; Rajesh Garg
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Nikhil Jayakumar; Suganth Paul; Rajesh Garg:
Minimizing and Exploiting Leakage in VLSI Design - nuovo livro

ISBN: 9781441909503

Engineering; Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design ASIC, EDA, Electronic Design Automation, Leakage, Low Power Design, Sub-threshold logic, Transistor, VL… mais…

  - This book presents two techniques to reduce leakage power in digital VLSI ICs. The first reduces leakage through the selective use of high threshold voltage sleep transistors, while the second by applying the optimal Reverse Body Bias voltage. Custos de envio:zzgl. Versandkosten., mais custos de envio
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Minimizing and Exploiting Leakage in VLSI Design - Hugo Pinto
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Hugo Pinto:
Minimizing and Exploiting Leakage in VLSI Design - nuovo livro

ISBN: 9781441909503

This book presents two techniques to reduce leakage power in digital VLSI ICs. The first reduces leakage through the selective use of high threshold voltage sleep transistors, while the s… mais…

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Minimizing and Exploiting Leakage in VLSI Design - Nikhil Jayakumar; Suganth Paul; Rajesh Garg
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Nikhil Jayakumar; Suganth Paul; Rajesh Garg:
Minimizing and Exploiting Leakage in VLSI Design - primeira edição

2009, ISBN: 9781441909503

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Minimizing and Exploiting Leakage in VLSI Design
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9781441909503

Dados detalhados do livro - Minimizing and Exploiting Leakage in VLSI Design


EAN (ISBN-13): 9781441909503
ISBN (ISBN-10): 1441909508
Ano de publicação: 2009
Editor/Editora: Springer-Verlag
214 Páginas
Língua: eng/Englisch

Livro na base de dados desde 2012-03-25T18:47:37-03:00 (Sao Paulo)
Página de detalhes modificada pela última vez em 2020-03-10T16:48:44-03:00 (Sao Paulo)
Número ISBN/EAN: 9781441909503

Número ISBN - Ortografia alternativa:
1-4419-0950-8, 978-1-4419-0950-3
Ortografia alternativa e termos de pesquisa relacionados:
Autor do livro: sunil, garg
Título do livro: vlsi, mini design

Dados da editora

Autor: Nikhil Jayakumar; Suganth Paul; Rajesh Garg
Título: Minimizing and Exploiting Leakage in VLSI Design
Editora: Springer; Springer US
214 Páginas
Ano de publicação: 2009-12-02
New York; NY; US
Língua: Inglês
106,99 € (DE)
110,00 € (AT)
130,00 CHF (CH)
Available
XXVII, 214 p.

EA; E107; eBook; Nonbooks, PBS / Technik/Elektronik, Elektrotechnik, Nachrichtentechnik; Schaltkreise und Komponenten (Bauteile); Verstehen; ASIC; EDA; Electronic Design Automation; Leakage; Low Power Design; Sub-threshold logic; Transistor; VLSI; VLSI Design; integrated circuit; C; Electronic Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design; Engineering; Computer-Aided Design (CAD); BC

Minimizing and Exploiting Leakage in VLSI Design Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati and Sunil P. Khatri Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents techniques aimed at reducing and exploiting leakage power in digital VLSI ICs. The first part of this book presents several approaches to reduce leakage in a circuit. The second part of this book shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic, with adaptive body bias to make the designs robust to variations. The third part of this book presents design and implementation details of a sub-threshold IC, using the ideas presented in the second part of this book. Provides a variety of approaches to control and exploit leakage, including implicit approaches to find the leakage of all input vectors in a design, techniques to find the minimum leakage vector of a design (with and without circuit modification), ASIC approaches to drastically reduce leakage, and methods to find the optimal reverse bias voltage to maximally reduce leakage. Presents a variation-tolerant, practical design methodology to implement sub-threshold logic using closed-loop adaptive body bias (ABB) and Network of PLA (NPLA) based design. In addition, asynchronous micropipelining techniques are presented, to substantially reclaim the speed penalty of sub-threshold design. Validates the proposed ABB and NPLA sub-threshold design approach by implementing a BFSK transmitter design in the proposed design style. Test results from the fabricated IC are provided as well, indicating that a power improvement of 20X can be obtained for a 0.25um process (projected power improvements are 100X to 500X for 65nm processes).
Provides a variety of approaches to control and exploit leakage Examines the issues with implementing sub-threshold logic and describes techniques to tackle these issues Presents a new, practical self-compensated, closed loop approach to controlling leakage, via sub-threshold circuits, which yields upwards of 20X power savings

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