ISBN: 9780387691671
Functional verification has become an important aspect of the chip design process. Significant resources, both in industry and academia, are devoted to the design complexity and verificat… mais…
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ISBN: 9780387691671
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2007, ISBN: 9780387691671
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ISBN: 9780387691671
Functional verification has become an important aspect of the chip design process. Significant resources, both in industry and academia, are devoted to the design complexity and verificat… mais…
ISBN: 9780387691671
SAT-Based Scalable Formal Verification Solutions: ab 106.99 € eBooks > Sachthemen & Ratgeber > Technik Springer-Verlag GmbH eBook als pdf, Springer-Verlag GmbH
ISBN: 9780387691671
; EPUB; Scientific, Technical and Medical > Electronics & communications engineering, Grand Central Publishing
2007, ISBN: 9780387691671
eBooks, eBook Download (PDF), Auflage, [PU: Springer-Verlag], [ED: 1], Springer-Verlag, 2007
2007, ISBN: 9780387691671
eBooks, eBook Download (PDF), 2007, [PU: Springer US], Springer US, 2007
Dados bibliográficos do melhor livro correspondente
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Dados detalhados do livro - SAT-Based Scalable Formal Verification Solutions
EAN (ISBN-13): 9780387691671
ISBN (ISBN-10): 0387691677
Ano de publicação: 2007
Editor/Editora: Springer US
330 Páginas
Língua: eng/Englisch
Livro na base de dados desde 2009-07-11T08:02:08-03:00 (Sao Paulo)
Página de detalhes modificada pela última vez em 2023-08-03T08:27:01-03:00 (Sao Paulo)
Número ISBN/EAN: 0387691677
Número ISBN - Ortografia alternativa:
0-387-69167-7, 978-0-387-69167-1
Ortografia alternativa e termos de pesquisa relacionados:
Autor do livro: mala gupta
Título do livro: scala, sat
Dados da editora
Autor: Malay Ganai; Aarti Gupta
Título: Series on Integrated Circuits and Systems; SAT-Based Scalable Formal Verification Solutions
Editora: Springer; Springer US
330 Páginas
Ano de publicação: 2007-05-26
New York; NY; US
Língua: Inglês
106,99 € (DE)
110,00 € (AT)
130,00 CHF (CH)
Available
XXX, 330 p. 118 illus.
EA; E107; eBook; Nonbooks, PBS / Informatik, EDV/Anwendungs-Software; Computer-Aided Design (CAD); Verstehen; algorithms; complexity; computer-aided design (CAD); design process; model; modeling; C; Computer-Aided Engineering (CAD, CAE) and Design; Electronic Circuits and Systems; Electrical and Electronic Engineering; Computer Science; Schaltkreise und Komponenten (Bauteile); Elektrotechnik; BC
Design Verification Challenges.- Design Verification Challenges.- Background.- Basic Infrastructure.- Efficient Boolean Representation.- Hybrid DPLL-Style SAT Solver.- Falsification.- SAT-Based Bounded Model Checking.- Distributed SAT-Based BMC.- Efficient Memory Modeling in BMC.- BMC for Multi-Clock Systems.- Proof Methods.- Proof by Induction.- Unbounded Model Checking.- Abstraction/Refinement.- Proof-Based Iterative Abstraction.- Verification Procedure.- SAT-Based Verification Framework.- Synthesis for Verification.Describes SAT-based model checking approaches and gives engineering details on what makes model checking practical Techniques covered can be synergistically combined into a scalabe solution Focuses on engineering design and not mathematics Includes supplementary material: sn.pub/extras;
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